Streaming SIMD Extensions enhance the
x86 architecture in four ways:
This set enables the
programmer to develop
algorithms that can mix packed, single-precision, floating-point and
using both SSE and MMX instructions respectively.
8 new 128-bit SIMD
that can be directly addressed;
50 new instructions
that work on packed floating-point
8 new instructions
designed to control
cacheability of all MMX and 32-bit x86 data types, including the
to stream data to memory without polluting the caches, and to prefetch
data before it is actually used;
12 new instructions
that extend the MMX instruction set.
This approach was chosen
media processing applications have the following characteristics:
Intel SSE provides eight
registers, each of which can be directly addressed using the register
XMM0 to XMM7. Each register consists of four 32-bit single precision,
numbers, numbered 0 through 3. MMX registers are mapped onto the
registers, requiring the EMMS instruction to pass from MMX code to x87
floating-point code; since SIMD floating-point registers are a separate
register file, MMX or floating-point instructions can be mixed with SSE
instructions without execution of a special instruction such as EMMS.
the downside, they require support from the operating system, since
must be saved when switching tasks.
wide dynamic range,
hence floating-point based
regular memory access
There is a new
MXCSR, that is used to mask/unmask numerical exception handling, to set
rounding modes, to set flush-to-zero mode, and to view status flags.
SSE instructions operate
on either all
or the least significant pairs of packed data operands in parallel. The
instructions (with PS suffix) operate on a pair of operands, while
instructions (with SS suffix) always operate on the least
pair of the two operands; for scalar operations, the three upper
from the first operand are passed through to the destination.
The SSE set consists of
the following sections give a brief overview of each group of
in the SSE set and the instructions within each group.