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    Despite the trend of doubling system performance every 1.5 to 2 years, current general purpose microprocessors have not met the requirements of the networking and telecommunications industry due to several emerging applications, such as the explosive growth of the Internet, digital cellular phones, IP-based telephony and wireless messaging. A general trend in the industry is using programmable processors to implement adaptive filters, modulators and demodulators.  The Motorola AltiVec technology is designed to be a single chip solution for high-bandwidth data processing and algorithmic intensive computations which today are typically handled off-chip by other devices, such as dedicated hardware, DSP farms or custom ASICs.
    The Motorola AltiVec technology expands the current PowerPC architecture through the addition of a 128-bit vector execution unit which operates concurrently with the existing integer and floating point units, so that the programmer can freely intermix PowerPC integer, floating-point and vector instructions.
    The AltiVec technology supports:
    • 16-way parallelism for 8-bit signed and unsigned integers
    • 8-way parallelism for 16-bit signed and unsigned integers
    • 4-way parallelism for 32-bit signed and unsigned integer and IEEE floating-point numbers
    The AltiVec technology also adds a separate register file containing 32 entries, each 128-bits wide, twice the size of MMX registers. These registers hold the data sources for the Altivec execution units, and are loaded from and stored to memory through vector load and vector store instructions. Each AltiVec instruction can specify up to three source operand and a single destination operand; all operand are vector registers, except for the load and store instructions and a few instruction types that provide operands from immediate fields. 
    The AltiVec technology introduces 162 new instructions, that can be divided into the following major classes:
    1. Intra-Element Arithmetic Operations: they perform indipendent parallel computations on the elements contained in the source vector registers and place the result in the corresponding fields of the destination vector register. These instructions support both saturation and modulo arithmetic, and both signed and unsigned integers and floating-point data types as operands. The AltiVec technology provides a wide set of intra-element operations: addition, subtraction, multiply, multiply and add, min, max, average, and conversions between floating-point and 32-bit integer data formats.
    2. Intra-Element Non-Arithmetic Operations: they include various forms of compare, shift, rotate, and the following logical operations: AND, OR, NOT, XOR, AND NOT. Comparison instructions between vectors or vector elements help rapidly generating masks or performing conditional tests that can change the programís flow. There is also a select instruction that is designed to choose source data from one of two source registers and transfer that data to the results register.
    3. Inter-Element Arithmetic Operations: the sum of products and sum across instructions allow for elements within a single vector register to be summed in combination with a separate accumulation register: these instructions greatly speed-up the computation of dot products which are the most common vector operation in engineering and scientific computations.
    4. Inter-Element Non-Arithmetic Operations: they include wide field shift operations, pack and unpack instructions, including a special instruction to handle the 1/5/5/5 pixel format commonly used for 16-bit color graphics, merge instructions that can interleave data at the byte, halfword and word level, and the permute operation, that is capable of taking any 16 8-bit elements from two sources and placing the bytes in any order in a destination register: this operation can, within a single cycle, let a network application extract an IP packetís header.
    The initial target application for the AltiVec technology include: IP telephony gateways, multi-channel modems, speech processing systems, echo cancelers, image and video processing systems, scientific array processing systems, as well as network infrastructure such as Internet routers and virtual private network servers.

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